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PCA9632
4-bit Fm+ I2C-bus low power LED driver
Rev. 01 -- 28 September 2007 Objective data sheet
1. General description
The PCA9632 is an I2C-bus controlled 4-bit LED driver optimized for Red/Green/Blue/Amber (RGBA) color mixing applications. The PCA9632 is a drop-in upgrade for the PCA9633 with 40x power reduction. In individual brightness control mode, each LED output has its own 8-bit resolution (256 steps) fixed frequency Individual PWM controller that operates at 1.5625 kHz with a duty cycle that is adjustable from 0 % to 99.6 % to allow the LED to be set to a specific brightness value. In group dimming mode, each LED output has its own 6-bit resolution (64 steps) fixed frequency Individual PWM controller that operates at 6.25 kHz with a duty cycle that is adjustable from 0 % to 98.4 % to allow the LED to be set to a specific brightness value. A fifth 4-bit resolution (16 steps) Group PWM controller has a fixed frequency of 190 Hz that is used to dim all the LEDs with the same value. While operating in the Blink mode, each LED output has its own 8-bit resolution (256 steps) fixed frequency individual PWM controller that operates at 1.5625 kHz with a duty cycle that is adjustable from 0 % to 99.6 % to allow the LED to be set to a specific brightness value. Blink rate is controlled by the Group Frequency setting that has 8-bit resolution (256 steps). The blink rate is adjustable between 24 Hz to once every 10.73 seconds. For Group Frequency settings between 6 Hz and 24 Hz, the Group PWM has a 6-bit resolution (64 steps) with a duty cycle that is adjustable from 0 % to 98.4 %. For Group frequency settings between 6 Hz to 0.09 Hz (once in 10.73 seconds), the Group PWM has an 8-bit resolution (256 steps) with a duty cycle that is adjustable from 0 % to 99.6 %. Each LED output can be off, on (no PWM control), set at its Individual PWM controller value or at both Individual and Group PWM controller values. The LED output driver is programmed to be either open-drain with a 25 mA current sink capability at 5 V or totem-pole with a 25 mA sink, 10 mA source capability at 5 V. The PCA9632 operates with a supply voltage range of 2.3 V to 5.5 V and the outputs are 5.5 V tolerant. LEDs can be directly connected to the LED output (up to 25 mA, 5.5 V) or controlled with external drivers and a minimum amount of discrete components for larger current or higher voltage LEDs. The PCA9632 is in the new Fast-mode Plus (Fm+) family. Fm+ devices offer higher frequency (up to 1 MHz) and more densely populated bus operation (up to 4000 pF). Software programmable LED Group and three Sub Call I2C addresses allow all or defined groups of PCA9632 devices to respond to a common I2C-bus address, allowing for example, all red LEDs to be turned on or off at the same time or marquee chasing effect, thus minimizing I2C-bus commands.
NXP Semiconductors
PCA9632
4-bit Fm+ I2C-bus low power LED driver
The Software Reset (SWRST) Call allows the master to perform a reset of the PCA9632 through the I2C-bus, identical to the Power-On Reset (POR) that initializes the registers to their default state causing the outputs to be set high-impedance. This allows an easy and quick way to reconfigure all device registers to the same condition.
2. Features
I 40x power reduction compared to PCA9633 I 4 LED drivers. Each output programmable at: N Off N On N Programmable LED brightness N Programmable group dimming/blinking mixed with individual LED brightness I 1 MHz Fast-mode Plus I2C-bus interface with 30 mA high drive capability on SDA output for driving high capacitive buses I 256-step (8-bit) linear programmable brightness per LED output varying from fully off (default) to maximum brightness using a 1.5625 kHz PWM signal in individual brightness mode I 64-step (6-bit) linear programmable brightness for each LED output varying from fully off (default) to maximum brightness using a 6.25 kHz PWM signal in Group dim mode I In group dim mode 16-step group brightness control allows global dimming (using a 190 Hz PWM signal) from fully off to maximum brightness (default) I 256-step (8-bit) linear programmable brightness per LED output varying from fully off (default) to maximum brightness using a 1.5625 kHz PWM signal in group blink mode I 64-step group blinking with frequency programmable from 24 Hz to 6 Hz and duty cycle from 0 % to 98.4 % I 256-step group blinking with frequency programmable from 6 Hz to 0.09 Hz (10.73 s) and duty cycle from 0 % to 99.6 % I Four totem-pole outputs (sink 25 mA and source 10 mA at 5 V) with software programmable open-drain LED outputs selection (default at high-impedance). No input function. I Output state change programmable on the Acknowledge or the STOP Command to update outputs byte-by-byte or all at the same time (default to `Change on STOP'). I Software Reset feature (SWRST Call) allows the device to be reset through the I2C-bus I 400 kHz internal oscillator requires no external components I Internal power-on reset I Noise filter on SDA/SCL inputs I Edge rate control on outputs I No glitch on power-up I Supports hot insertion I Low standby current of < 1 A I Operating power supply voltage range of 2.3 V to 5.5 V I 5.5 V tolerant inputs I -40 C to +85 C operation I ESD protection exceeds 5000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101
PCA9632_1 (c) NXP B.V. 2007. All rights reserved.
Objective data sheet
Rev. 01 -- 28 September 2007
2 of 32
NXP Semiconductors
PCA9632
4-bit Fm+ I2C-bus low power LED driver
I Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA I Packages offered: TSSOP8, HVSON8
3. Applications
I I I I I RGB or RGBA LED drivers for color mixing LED status information LED displays LCD backlights Keypad backlights for cellular phones or handheld devices
4. Ordering information
Table 1. Ordering information Topside mark 9632 9632 Package Name TSSOP8 HVSON8 Description plastic thin shrink small outline package; 8 leads; body width 3 mm plastic thermal enhanced very thin small outline package; no leads; 8 terminals; body 3 x 3 x 0.85 mm Version SOT505-1 SOT908-1 Type number PCA9632DP1 PCA9632TK
5. Block diagram
PCA9632
SCL SDA I2C-BUS CONTROL VDD VSS POWER-ON RESET LED STATE SELECT REGISTER PWM REGISTER X BRIGHTNESS CONTROL 24 Hz to 0.09 Hz GRPPWM REGISTER '0' - permanently OFF '1' - permanently ON
002aad039
INPUT FILTER
VDD
LEDn
6.25 kHz/ 1.56 kHz 400 kHz OSCILLATOR
GRPFREQ REGISTER
MUX/ CONTROL
190 Hz
Fig 1. Block diagram of PCA9632
PCA9632_1 (c) NXP B.V. 2007. All rights reserved.
Objective data sheet
Rev. 01 -- 28 September 2007
3 of 32
NXP Semiconductors
PCA9632
4-bit Fm+ I2C-bus low power LED driver
6. Pinning information
6.1 Pinning
terminal 1 index area LED0 LED1 LED0 LED1 LED2 LED3 1 2 3 4
002aad040
1 2
8 7
VDD SDA SCL VSS
PCA9632TK
8 7 VDD SDA SCL VSS LED3 4 5 LED2 3 6
PCA9632DP1
6 5
002aad041
Transparent top view
Fig 2. Pin configuration for TSSOP8
Fig 3. Pin configuration for HVSON8
6.2 Pin description
Table 2. Symbol LED0 LED1 LED2 LED3 VSS SCL SDA VDD
[1]
Pin description Pin 1 2 3 4 5[1] 6 7 8 Type O O O O power supply I I/O power supply Description LED driver 0 LED driver 1 LED driver 2 LED driver 3 supply ground serial clock line serial data line supply voltage
HVSON package die supply ground is connected to both the VSS pin and the exposed center pad. The VSS pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board-level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias need to be incorporated in the PCB in the thermal pad region.
PCA9632_1
(c) NXP B.V. 2007. All rights reserved.
Objective data sheet
Rev. 01 -- 28 September 2007
4 of 32
NXP Semiconductors
PCA9632
4-bit Fm+ I2C-bus low power LED driver
7. Functional description
Refer to Figure 1 "Block diagram of PCA9632".
7.1 Device addresses
Following a START condition, the bus master must output the address of the slave it is accessing.
7.1.1 Regular I2C-bus slave address
The I2C-bus slave address of the PCA9632 is shown in Figure 4.
slave address 1 1 0 0 fixed 0 1 0 R/W
002aab318
Fig 4. Slave address
The last bit of the address byte defines the operation to be performed. When set to logic 1 a read is selected, while a logic 0 selects a write operation.
7.1.2 LED All Call I2C-bus address
* Default power-up value (ALLCALLADR register): E0h or 1110 000 * Programmable through I2C-bus (volatile programming) * At power-up, LED All Call I2C-bus address is enabled. PCA9632 sends an ACK when
E0h (R/W = 0) or E1h (R/W = 1) is sent by the master. See Section 7.3.8 "LED All Call I2C-bus address, ALLCALLADR" for more detail. Remark: The default LED All Call I2C-bus address (E0h or 1110 000) must not be used as a regular I2C-bus slave address since this address is enabled at power-up. All the PCA9632s on the I2C-bus will acknowledge the address if sent by the I2C-bus master.
7.1.3 LED Sub Call I2C-bus addresses
* 3 different I2C-bus addresses can be used * Default power-up values:
- SUBADR1 register: E2h or 1110 001 - SUBADR2 register: E4h or 1110 010 - SUBADR3 register: E8h or 1110 100
* Programmable through I2C-bus (volatile programming) * At power-up, Sub Call I2C-bus addresses are disabled. PCA9632 does not send an
ACK when E2h (R/W = 0) or E3h (R/W = 1), E4h (R/W = 0) or E5h (R/W = 1), or E8h (R/W = 0) or E9h (R/W = 1) is sent by the master. See Section 7.3.7 "I2C-bus subaddress 1 to 3, SUBADRx" for more detail.
PCA9632_1
(c) NXP B.V. 2007. All rights reserved.
Objective data sheet
Rev. 01 -- 28 September 2007
5 of 32
NXP Semiconductors
PCA9632
4-bit Fm+ I2C-bus low power LED driver
Remark: The default LED Sub Call I2C-bus addresses may be used as regular I2C-bus slave addresses as long as they are disabled.
7.1.4 Software Reset I2C-bus address
The address shown in Figure 5 is used when a reset of the PCA9632 needs to be performed by the master. The Software Reset address (SWRST Call) must be used with R/W = 0. If R/W = 1, the PCA9632 does not acknowledge the SWRST. See Section 7.5 "Software Reset" for more detail.
R/W 0 0 0 0 0 1 1 0
002aab416
Fig 5. Software Reset address
Remark: The Software Reset I2C-bus address is a reserved address and cannot be used as a regular I2C-bus slave address or as an LED All Call or LED Sub Call address.
7.2 Control register
Following the successful acknowledgement of the slave address, LED All Call address or LED Sub Call address, the bus master will send a byte to the PCA9632, which will be stored in the Control register. The lowest 4 bits are used as a pointer to determine which register will be accessed (D[3:0]). The highest 3 bits are used as Auto-Increment flag and Auto-Increment options (AI[2:0]). Bit 4 is unused and must be programmed with zero (0) for proper device operation.
register address AI2 AI1 AI0 0 D3 D2 D1 D0
002aab296
Auto-Increment options Auto-Increment flag
reset state = 80h Remark: The Control register does not apply to the Software Reset I2C-bus address.
Fig 6. Control register
When the Auto-Increment flag is set (AI2 = 1), the four low order bits of the Control register are automatically incremented after a read or write. This allows the user to program the registers sequentially. Four different types of Auto-Increment are possible, depending on AI1 and AI0 values.
PCA9632_1
(c) NXP B.V. 2007. All rights reserved.
Objective data sheet
Rev. 01 -- 28 September 2007
6 of 32
NXP Semiconductors
PCA9632
4-bit Fm+ I2C-bus low power LED driver
Auto-Increment options AI1 0 0 0 1 1 AI0 0 0 1 0 1 Function no Auto-Increment Auto-Increment for all registers. D3, D2, D1, D0 roll over to `0000' after the last register (1100) is accessed. Auto-Increment for individual brightness registers only. D3, D2, D1, D0 roll over to `0010' after the last register (0101) is accessed. Auto-Increment for global control registers only. D3, D2, D1, D0 roll over to `0110' after the last register (0111) is accessed. Auto-Increment for individual and global control registers only. D3, D2, D1, D0 roll over to `0010' after the last register (0111) is accessed.
Table 3. AI2 0 1 1 1 1
Remark: Other combinations not shown in Table 3 (AI[2:0] = 001, 010, and 011) are reserved and must not be used for proper device operation. AI[2:0] = 000 is used when the same register must be accessed several times during a single I2C-bus communication, for example, changes the brightness of a single LED. Data is overwritten each time the register is accessed during a write operation. AI[2:0] = 100 is used when all the registers must be sequentially accessed, for example, power-up programming. AI[2:0] = 101 is used when the four LED drivers must be individually programmed with different values during the same I2C-bus communication, for example, changing color setting to another color setting. AI[2:0] = 110 is used when the LED drivers must be globally programmed with different settings during the same I2C-bus communication, for example, global brightness or blinking change. AI[2:0] = 111 is used when individual and global changes must be performed during the same I2C-bus communication, for example, changing a color and global brightness at the same time. Only the 4 least significant bits D[3:0] are affected by the AI[2:0] bits. When the Control register is written, the register entry point determined by D[3:0] is the first register that will be addressed (read or write operation), and can be anywhere between 0000 and 1100 (as defined in Table 4). When AI[2] = 1, the Auto-Increment flag is set and the rollover value at which the point where the register increment stops and goes to the next one is determined by AI[2:0]. See Table 3 for rollover values. For example, if the Control register = 1110 1000 (E8h), then the register addressing sequence will be (in hex): 08 ... 0C 00 ... 07 02 ... 07 02 ... 07 02 ... as long as the master keeps sending or reading data.
PCA9632_1
(c) NXP B.V. 2007. All rights reserved.
Objective data sheet
Rev. 01 -- 28 September 2007
7 of 32
NXP Semiconductors
PCA9632
4-bit Fm+ I2C-bus low power LED driver
7.3 Register definitions
Table 4. 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch
[1] [2]
Register summary[1][2] D3 0 0 0 0 0 0 0 0 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 Name MODE1 MODE2 PWM0 PWM1 PWM2 PWM3 GRPPWM GRPFREQ LEDOUT SUBADR1 SUBADR2 SUBADR3 ALLCALLADR Type read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write Function Mode register 1 Mode register 2 brightness control LED0 brightness control LED1 brightness control LED2 brightness control LED3 group duty cycle control group frequency LED output state I2C-bus subaddress 1 I2C-bus subaddress 2 I2C-bus subaddress 3 LED All Call I2C-bus address
Register number (hex)
Only D[3:0] = 0000 to 1100 are allowed and will be acknowledged. D[3:0] = 1101, 1110, or 1111 are reserved and will not be acknowledged. When writing to the Control register, bit 4 must be programmed with logic 0 for proper device operation.
7.3.1 Mode register 1, MODE1
Table 5. MODE1 - Mode register 1 (address 00h) bit description Legend: * default value. Bit 7 6 5 4 3 2 1 0 Symbol AI2 AI1 AI0 SLEEP SUB1 SUB2 SUB3 ALLCALL Access read only read only read only R/W R/W R/W R/W R/W Value 0 1* 0* 1 0* 1 0 1* 0* 1 0* 1 0* 1 0 1*
[1] [2]
Description Register Auto-Increment disabled Register Auto-Increment enabled Auto-Increment bit 1 = 0 Auto-Increment bit 1 = 1 Auto-Increment bit 0 = 0 Auto-Increment bit 0 = 1 Normal mode[1]. Low power mode. Oscillator off[2]. PCA9632 does not respond to I2C-bus subaddress 1. PCA9632 responds to I2C-bus subaddress 1. PCA9632 does not respond to I2C-bus subaddress 2. PCA9632 responds to I2C-bus subaddress 2. PCA9632 does not respond to I2C-bus subaddress 3. PCA9632 responds to I2C-bus subaddress 3. PCA9632 does not respond to LED All Call I2C-bus address. PCA9632 responds to LED All Call I2C-bus address.
It takes 500 s max. for the oscillator to be up and running once SLEEP bit has been set to logic 1. Timings on LEDn outputs are not guaranteed if PWMx, GRPPWM or GRPFREQ registers are accessed within the 500 s window. No blinking or dimming is possible when the oscillator is off.
(c) NXP B.V. 2007. All rights reserved.
PCA9632_1
Objective data sheet
Rev. 01 -- 28 September 2007
8 of 32
NXP Semiconductors
PCA9632
4-bit Fm+ I2C-bus low power LED driver
7.3.2 Mode register 2, MODE2
Table 6. MODE2 - Mode register 2 (address 01h) bit description Legend: * default value. Bit 7 6 5 4 3 2 1 to 0
[1] [2]
Symbol DMBLNK INVRT[1] OCH OUTDRV[1] OUTNE[1:0]
Access read only read only R/W R/W R/W R/W R/W
Value 0* 0* 0* 1 0* 1 0* 1 0* 1 01*
Description reserved reserved Group control = dimming Group control = blinking Output logic state not inverted. Value to use when no external driver used. Output logic state inverted. Value to use when external driver used. Outputs change on STOP command.[2] Outputs change on ACK. The 4 LED outputs are configured with an open-drain structure. The 4 LED outputs are configured with a totem-pole structure. unused
See Section 7.6 "Using the PCA9632 with and without external drivers" for more details. Change of the outputs at the STOP command allows synchronizing outputs of more than one PCA9632. Applicable to registers from 02h (PWM0) to 08h (LEDOUT) only.
7.3.3 PWM registers 0 to 3, PWMx--Individual brightness control registers
Table 7. PWM0 to PWM3 - PWM registers 0 to 3 (address 02h to 05h) bit description Legend: * default value. Address 02h 03h 04h 05h Register PWM0 PWM1 PWM2 PWM3 Bit 7:0 7:0 7:0 7:0 Symbol IDC0[7:0] IDC1[7:0] IDC2[7:0] IDC3[7:0] Access Value R/W R/W R/W R/W Description 0000 0000* PWM0 Individual Duty Cycle 0000 0000* PWM1 Individual Duty Cycle 0000 0000* PWM2 Individual Duty Cycle 0000 0000* PWM3 Individual Duty Cycle
While operating in Individual brightness mode (LDRx = 10), a 1.5625 kHz fixed frequency signal is used for each output. Duty cycle is controlled through 256 linear steps from 00h (0 % duty cycle = LED output off) to FFh (99.6 % duty cycle = LED output at maximum brightness). In this mode, all the 8 bits are used. IDCx [ 7:0 ] duty cycle = -------------------------256 E.g., if IDCx[7:0] = 1111 1111, then duty cycle = 255 / 256 = 99.6 %. While operating in Group dim mode, a 6.25 kHz fixed frequency signal is used for each output. Duty cycle is controlled through 64 linear steps from 00h (0 % duty cycle = LED output off) to 3Fh (98.4 % duty cycle = LED output at maximum brightness). In this mode only the 6 MSBs are used (IDCx[7:2]). The 2 LSBs IDCx[1:0] are ignored. Applicable to LED outputs programmed with LDRx = 11 (LEDOUT register). IDCx [ 7:2 ],00 duty cycle = ----------------------------------256 E.g., if IDCx[7:2] = 111111, then duty cycle = 1111 1100 / 256 = 252 / 256 = 98.4 %.
PCA9632_1 (c) NXP B.V. 2007. All rights reserved.
(1)
(2)
Objective data sheet
Rev. 01 -- 28 September 2007
9 of 32
NXP Semiconductors
PCA9632
4-bit Fm+ I2C-bus low power LED driver
While operating in blink mode, a 1.5625 kHz fixed frequency signal is used for each output. Duty cycle is controlled through 256 linear steps from 00h (0 % duty cycle = LED output off) to FFh (99.6 % duty cycle = LED output at maximum brightness). In this mode, all the 8 bits are used. IDCx [ 7:0 ] duty cycle = -------------------------256 E.g., if IDCx[7:0] = 1111 1111, then duty cycle = 255 / 256 = 99.6 %. Applicable to LED outputs programmed with LDRx = 11 (LEDOUT register). (3)
7.3.4 Group duty cycle control, GRPPWM
Table 8. GRPPWM - Group duty cycle control register (address 06h) bit description Legend: * default value. Address 06h Register GRPPWM Bit 7:0 Symbol GDC[7:0] Access R/W Value 1111 1111 Description GRPPWM register
When DMBLNK bit (MODE2 register) is programmed with 0, a 190 Hz fixed frequency signal is superimposed with the 6.25 kHz individual brightness control signal. GRPPWM is then used as a global brightness control allowing the LED outputs to be dimmed with the same value. The value in GRPFREQ is then a `Don't care'. In the group dim mode (DMBLNK = 0) global brightness for the 4 outputs is controlled through 16 linear steps from 00h (0 % duty cycle = LED output off) to F0h (93.75 % duty cycle = maximum brightness). In this mode only the 4 MSBs of the GRPPWM[7:4] are used. Bits GRPPWM[3:0] are unused. GDC [ 7:4 ],0000 duty cycle = ---------------------------------------256 E.g., if GDC[7:4] = 1111, then duty cycle = 1111 0000 / 256 = 240 / 256 = 93.75 %. When DMBLNK bit is programmed with 1, GRPPWM and GRPFREQ registers define a global blinking pattern, where GRPFREQ contains the blinking period (from 24 Hz to 10.73 s) and GRPPWM the duty cycle (ON/OFF ratio in %). In this mode, when GRPFREQ is programmed to provide a blinking with frequency programmable from 24 Hz to 6 Hz, GRPPWM[7:2] is used to provide 64-step duty cycle resolution from 0 % to 98.4 %. GRPPWM[1:0] bits are unused. GDC [ 7:2 ],00 duty cycle = ---------------------------------256 E.g., if GDC[7:2] = 111111, then duty cycle = 1111 1100 / 256 = 252 / 256 = 98.4 %. When GRPFREQ is programmed to provide a blinking with frequency programmable from 6 Hz to 0.09 Hz (10.73 s), GRPPWM[7:0] is used to provide a 256-step duty cycle resolution from 0 % to 99.6 %. In this case, all the 8 bits of the GRPPWM register are used. GDC [ 7:0 ] duty cycle = -------------------------256
PCA9632_1
(4)
(5)
(6)
(c) NXP B.V. 2007. All rights reserved.
Objective data sheet
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NXP Semiconductors
PCA9632
4-bit Fm+ I2C-bus low power LED driver
E.g., If GDC[7:0] = 1111 1111, then duty cycle = 255 / 256 = 99.6 %. Applicable to LED outputs programmed with LDRx = 11 (LEDOUT register).
7.3.5 Group frequency, GRPFREQ
Table 9. GRPFREQ - Group Frequency register (address 07h) bit description Legend: * default value. Address 07h Register GRPFREQ Bit 7:0 Symbol GFRQ[7:0] Access R/W Value 0000 0000* Description GRPFREQ register
GRPFREQ is used to program the global blinking period when DMBLNK bit (MODE2 register) is equal to 1. Value in this register is a `Don't care' when DMBLNK = 0. Applicable to LED outputs programmed with LDRx = 11 (LEDOUT register). Blinking period is controlled through 256 linear steps from 00h (41 ms, frequency 24 Hz) to FFh (10.73 seconds). GFRQ [ 7:0 ] + 1 global blinking period = --------------------------------------- ( in sec onds ) 24 (7)
7.3.6 LED driver output state, LEDOUT
Table 10. LEDOUT - LED driver output state register (address 08h) bit description Legend: * default value. Address 08h Register LEDOUT Bit 7:6 5:4 3:2 1:0 Symbol LDR3 LDR2 LDR1 LDR0 Access R/W R/W R/W R/W Value 00* 00* 00* 00* Description LED3 output state control LED2 output state control LED1 output state control LED0 output state control
LDRx = 00 -- LED driver x is off (default power-up state). LDRx = 01 -- LED driver x is fully on (individual brightness and group dimming/blinking not controlled). LDRx = 10 -- LED driver x individual brightness can be controlled through its PWMx register. LDRx = 11 -- LED driver x individual brightness and group dimming/blinking can be controlled through its PWMx register and the GRPPWM registers.
7.3.7 I2C-bus subaddress 1 to 3, SUBADRx
SUBADR1 to SUBADR3 - I2C-bus subaddress registers 0 to 3 (address 09h to 0Bh) bit description Legend: * default value. Table 11. Address 09h 0Ah 0Bh Register SUBADR1 SUBADR2 SUBADR3 Bit 7:1 0 7:1 0 7:1 0
PCA9632_1
Symbol A1[7:1] A1[0] A2[7:1] A2[0] A3[7:1] A3[0]
Access Value R/W R only R/W R only R/W R only 1110 001* 0* 1110 010* 0* 1110 100* 0*
Description I2C-bus subaddress 1 reserved I2C-bus subaddress 2 reserved I2C-bus subaddress 3 reserved
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Objective data sheet
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NXP Semiconductors
PCA9632
4-bit Fm+ I2C-bus low power LED driver
Subaddresses are programmable through the I2C-bus. Default power-up values are E2h, E4h, E8h, and the device(s) will not acknowledge these addresses right after power-up (the corresponding SUBx bit in MODE1 register is equal to 0). Once subaddresses have been programmed to their right values, SUBx bits need to be set to 1 in order to have the device acknowledging these addresses (MODE1 register). Only the 7 MSBs representing the I2C-bus subaddress are valid. The LSB in SUBADRx register is a read-only bit (0). When SUBx is set to 1, the corresponding I2C-bus subaddress can be used during either an I2C-bus read or write sequence.
7.3.8 LED All Call I2C-bus address, ALLCALLADR
ALLCALLADR - LED All Call I2C-bus address register (address 0Ch) bit description Legend: * default value. Table 12. Address 0Ch Register ALLCALLADR Bit 7:1 0 Symbol AC[7:1] AC[0] Access Value R/W R only 1110 000* 0* Description ALLCALL I2C-bus address register reserved
The LED All Call I2C-bus address allows all the PCA9632s in the bus to be programmed at the same time (ALLCALL bit in register MODE1 must be equal to 1, power-up default state). This address is programmable through the I2C-bus and can be used during either an I2C-bus read or write sequence. The register address can be programmed as a sub call. Only the 7 MSBs representing the All Call I2C-bus address are valid. The LSB in ALLCALLADR register is a Read-only bit (0). If ALLCALL bit = 0, the device does not acknowledge the address programmed in register ALLCALLADR.
7.4 Power-on reset
When power is applied to VDD, an internal Power-on reset holds the PCA9632 in a reset condition until VDD has reached VPOR. At this point, the reset condition is released and the PCA9632 registers and I2C-bus state machine are initialized to their default states (all zeroes) causing all the channels to be deselected. Thereafter, VDD must be lowered below 0.2 V to reset the device.
PCA9632_1
(c) NXP B.V. 2007. All rights reserved.
Objective data sheet
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NXP Semiconductors
PCA9632
4-bit Fm+ I2C-bus low power LED driver
7.5 Software Reset
The Software Reset Call (SWRST Call) allows all the devices in the I2C-bus to be reset to the power-up state value through a specific formatted I2C-bus command. To be performed correctly, it implies that the I2C-bus is functional and that there is no device hanging the bus. The SWRST Call function is defined as the following: 1. A START command is sent by the I2C-bus master. 2. The reserved SWRST I2C-bus address `0000 011' with the R/W bit set to 0 (write) is sent by the I2C-bus master. 3. The PCA9632 device(s) acknowledge(s) after seeing the SWRST Call address `0000 0110' (06h) only. If the R/W bit is set to 1 (read), no acknowledge is returned to the I2C-bus master. 4. Once the SWRST Call address has been sent and acknowledged, the master sends 2 bytes with 2 specific values (SWRST data byte 1 and byte 2): a. Byte 1 = A5h: the PCA9632 acknowledges this value only. If byte 1 is not equal to A5h, the PCA9632 does not acknowledge it. b. Byte 2 = 5Ah: the PCA9632 acknowledges this value only. If byte 2 is not equal to 5Ah, then the PCA9632 does not acknowledge it. If more than 2 bytes of data are sent, the PCA9632 does not acknowledge any more. 5. Once the right 2 bytes (SWRST data byte 1 and byte 2 only) have been sent and correctly acknowledged, the master sends a STOP command to end the SWRST Call: the PCA9632 then resets to the default value (power-up value) and is ready to be addressed again within the specified bus free time (tBUF). The I2C-bus master must interpret a non-acknowledge from the PCA9632 (at any time) as a `SWRST Call Abort'. The PCA9632 does not initiate a reset of its registers. This happens only when the format of the SWRST Call sequence is not correct.
7.6 Using the PCA9632 with and without external drivers
The PCA9632 LED output drivers are 5.5 V only tolerant and can sink up to 25 mA at 5 V. If the device needs to drive LEDs to a higher voltage and/or higher current, use of an external driver is required.
* INVRT bit (MODE2 register) can be used to keep the LED PWM control firmware the
same (PWMx and GRPPWM values directly calculated from their respective formulas and the LED output state determined by LEDOUT register value) independently of the type of external driver.
* OUTDRV bit (MODE2 register) allows minimizing the amount of external components
required to control the external driver (N-type or P-type device).
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4-bit Fm+ I2C-bus low power LED driver
Table 13.
Use of INVRT and OUTDRV based on connection to the LEDn outputs External N-type driver Firmware External pull-up resistor External P-type driver Firmware External pull-up resistor Firmware External pull-up resistor
INVRT OUTDRV Direct connection to LEDn
0
0
formulas and LED output state values apply[1] formulas and LED output state values apply[1] formulas and LED output state values inverted formulas and LED output state values inverted
LED current formulas and LED required limiting R[1] output state values inverted
formulas and LED required output state values apply
0
1
LED current formulas and LED not required formulas and LED not limiting R[1] output state output state values required[3] values inverted apply[3] LED current formulas and LED required limiting R output state values apply LED current formulas and LED not limiting R output state required[2] values apply[2] formulas and LED required output state values inverted formulas and LED not required output state values inverted
1
0
1
1
[1] [2] [3]
Correct configuration when LEDs directly connected to the LEDn outputs (connection to VDD through current limiting resistor). Optimum configuration when external N-type (NPN, NMOS) driver used. Optimum configuration when external P-type (PNP, PMOS) driver used.
Table 14. LEDOUT 00
Output transistors based on LEDOUT registers, INVRT and OUTDRV bits INVRT 0 0 1 1 OUTDRV Upper transistor Lower transistor (LEDn to (VDD to LEDn) VSS) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 off on off off off off off on off Individual PWM (non-inverted) off Individual PWM (inverted) off Individual PWM (non-inverted) off Individual PWM (inverted) off off on on on on off off LEDn state high-Z[1] VDD VSS VSS VSS VSS high-Z[1] VDD
LED driver off
01 LED driver on
0 0 1 1
10 Individual brightness control
0 0 1 1
Individual PWM (non-inverted) VSS or high-Z[1] = PWMx value Individual PWM (non-inverted) VSS or VDD = PWMx value Individual PWM (inverted) Individual PWM (inverted) Individual + Group PWM (non-inverted) high-Z[1] or VSS = 1 - PWMx value VDD or VSS = 1 - PWMx value VSS or high-Z[1] = PWMx/GRPPWM values
11 Individual + Group dimming/ blinking
0 0 1 1
Individual PWM (non-inverted) VSS or VDD = PWMx/GRPPWM values Individual + Group PWM (inverted) Individual PWM (inverted) high-Z[1] or VSS = (1 - PWMx) or (1 - GRPPWM) values VDD or VSS = (1 - PWMx) or (1 - GRPPWM) values
[1]
External pull-up or LED current limiting resistor connects LEDn to VDD.
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4-bit Fm+ I2C-bus low power LED driver
7.7 Individual brightness control with group dimming/blinking
A 1.5625 kHz fixed frequency signal with programmable duty cycle (8 bits, 256 steps) is used to control individually the brightness for each LED. On top of this signal, one of the following signals can be superimposed (this signal can be applied to the 4 LED outputs):
* A lower 190 Hz fixed frequency signal with programmable duty cycle (4 bits, 16 steps)
is used to provide a global brightness control.
* A programmable frequency signal from 24 Hz to 110.73 Hz (8 bits, 256 steps) with
programmable duty cycle (6 bits, 64 steps) is used to provide a global blinking control for (24 Hz to 6 Hz) and (8 bits, 256 steps) for (6 Hz to 110.73 Hz).
1
2
3
4
5
6
7
8
9 10 11 12
507
508
509
510
511
512
1
2
3
4
5
6
7
8
9 10 11
Brightness Control signal (LEDn) N x 2.5 s with N = (0 to 256) (PWMx Register) 256 x 2.5 s = 640 s (1.5625 kHz)
002aad101
Minimum pulse width for LEDn Brightness Control is 2.5 s.
Fig 7. Individual LED Brightness Control signals
1
2
3
4
5
6
7
8
9 10 11 12
507
508
509
510
511
512
1
2
3
4
5
6
7
8
9 10 11
Brightness Control signal (LEDn) N x 2.5 s with N = (0 to 64) (PWMx Register) 64 x 2.5 s = 160 s (6.25 kHz)
M x 16 x 2 x 2.5 s with M = (1 to 16) (GRPPWM Register)
Group Dimming signal 16 x 2 x 256 x 2.5 s = 5.24 ms (190.7 Hz) 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
resulting Brightness + Group Dimming signal
002aad042
Minimum pulse width for LEDn Brightness Control is 2.5 s. Minimum pulse width for Group Dimming is 80 s. When M = 1 (GRPPWM register value), the resulting LEDn Brightness Control + Group Dimming signal will have 2 pulses of the LED Brightness Control signal (pulse width = N x 2.5 s, with `N' defined in PWMx register).
Fig 8. Brightness + Group Dimming signals
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4-bit Fm+ I2C-bus low power LED driver
Table 15.
Dimming and blinking resolution LDRx DMBLNK X 0 1 1 GRPPWM X 16 steps 64 steps 256 steps GRPFREQ X X 256 steps 256 steps Frequency 1.5625 kHz 190 Hz with 6.25 kHz modulation blink frequency = 6 Hz to 24 Hz PWMx frequency = 1.5625 kHz blink frequency = 0.09 Hz to 6 Hz PWMx frequency = 1.5625 kHz PWMx 256 steps 64 steps 256 steps 256 steps
Type of control
Individual LED brightness 10 without dimming Individual LED brightness 11 with global dimming Blinking (fast) Blinking (slow) 11 11
8. Characteristics of the I2C-bus
The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy.
8.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see Figure 9).
SDA
SCL data line stable; data valid change of data allowed
mba607
Fig 9. Bit transfer
8.1.1 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P) (see Figure 10.)
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SDA
SDA
SCL S START condition P STOP condition
SCL
mba608
Fig 10. Definition of START and STOP conditions
8.2 System configuration
A device generating a message is a `transmitter'; a device receiving is the `receiver'. The device that controls the message is the `master' and the devices which are controlled by the master are the `slaves' (see Figure 11).
SDA SCL MASTER TRANSMITTER/ RECEIVER SLAVE RECEIVER SLAVE TRANSMITTER/ RECEIVER MASTER TRANSMITTER MASTER TRANSMITTER/ RECEIVER I2C-BUS MULTIPLEXER
SLAVE
002aaa966
Fig 11. System configuration
8.3 Acknowledge
The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse; set-up time and hold time must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition.
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4-bit Fm+ I2C-bus low power LED driver
data output by transmitter not acknowledge data output by receiver acknowledge SCL from master S START condition 1 2 8 clock pulse for acknowledgement
002aaa987
9
Fig 12. Acknowledgement on the I2C-bus
9. Bus transactions
data for register D3, D2, D1, D0(1) A acknowledge from slave STOP condition
002aad043
slave address S 1 1 0 0 0 1 0 0 R/W A X X
control register X 0 D3 D2 D1 D0 A
P
START condition
Auto-Increment options Auto-Increment flag acknowledge from slave
acknowledge from slave
(1) See Table 4 for register definition.
Fig 13. Write to a specific register
slave address S 1 1 0 0 0 1 0 0 R/W acknowledge from slave SUBADR3 register (cont.) A acknowledge from slave A 1 0
control register 0 0 0 0 0 0 A
MODE1 register A acknowledge from slave
MODE2 register A acknowledge from slave (cont.)
START condition
Auto-Increment on all registers Auto-Increment on
MODE1 register selection
acknowledge from slave
ALLCALLADR register A acknowledge from slave STOP condition
002aad044
P
Fig 14. Write to all registers using the Auto-Increment feature
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4-bit Fm+ I2C-bus low power LED driver
slave address S 1 1 0 0 0 1 0 0 R/W acknowledge from slave PWM2 register (cont.) A acknowledge from slave A 1 0
control register 1 0 0 0 1 0 A
PWM0 register A acknowledge from slave
PWM1 register A acknowledge from slave (cont.)
START condition
increment on Individual brightness registers only Auto-Increment on
PWM0 register selection
acknowledge from slave
PWM3 register A acknowledge from slave
PWM0 register A acknowledge from slave
PWMx register A acknowledge from slave STOP condition
002aad045
P
Fig 15. Multiple writes to Individual Brightness registers only using the Auto-Increment feature
slave address S 1 1 0 0 0 1 0 0 R/W acknowledge from slave A 1 0
control register 0 0 0 0 0 0
ReSTART condition
slave address(1) A
data from MODE1 register A (cont.) acknowledge from master
A Sr A6 A5 A4 A3 A2 A1 A0 1 acknowledge from slave R/W
START condition
Auto-Increment on all registers Auto-Increment on
MODE1 register selection
acknowledge from slave data from MODE1 register A
data from MODE2 register (cont.) A
data from PWM0 A
data from ALLCALLADR register
A (cont.)
acknowledge from master data from last read byte (cont.) A P
acknowledge from master
acknowledge from master
acknowledge from master
not acknowledge from master
STOP condition
002aad046
Fig 16. Read all registers using the Auto-Increment feature
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4-bit Fm+ I2C-bus low power LED driver
slave address sequence (A) S 1 1 0 0 0 1 0 0 R/W acknowledge from slave A X X
control register X 0 1 1 0 0 A
new LED All Call I2C address(1) 1 0 1 0 1 0 1 X A P
START condition
ALLCALLADR register selection acknowledge from slave Auto-Increment on
acknowledge from slave STOP condition
the 16 LEDs are on at the acknowledge(2) LED All Call I2C address sequence (B) S 1 0 1 0 1 0 1 0 R/W acknowledge from the 4 devices A X X control register X 0 1 0 0 0 A LEDOUT register (LED fully ON) 0 1 0 1 0 1 0 1 A P
START condition
LEDOUT register selection acknowledge from the 4 devices
acknowledge from the 4 devices STOP condition
002aad047
(1) ALLCALL bit in MODE1 register is equal to 1 for this example. (2) OCH bit in MODE2 register is equal to 1 for this example.
Fig 17. LED All Call I2C-bus address programming and LED All Call sequence example
SWRST Call I2C address S 0 0 0 0 0 1 1 0 R/W acknowledge from slave(s) A 1 0
SWRST data Byte 1 = 0xA5 1 0 0 1 0 1 A 0 1
SWRST data Byte 2 = 0x5A 0 1 1 0 1 0 A P
START condition
acknowledge from slave(s)
acknowledge from slave(s)
PCA9632 is(are) reset. Registers are set to default power-up values.
002aad048
Fig 18. Software Reset (SWRST) Call sequence
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10. Application design-in information
5V VDD = 2.5 V, 3.3 V or 5.0 V 12 V
I2C-BUS/SMBus MASTER SDA SCL
10 k
10 k
VDD SDA SCL LED0 LED1 LED2
PCA9632
VSS LED3
002aad049
I2C-bus address = 1100 010x.
Fig 19. Typical application
11. Limiting values
Table 16. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD VI/O IO(LEDn) ISS Ptot Tstg Tamb Parameter supply voltage voltage on an input/output pin output current on pin LEDn ground supply current total power dissipation storage temperature ambient temperature operating Conditions Min -0.5 VSS - 0.5 -65 -40 Max +6.0 5.5 25 100 400 +150 +85 Unit V V mA mA mW C C
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12. Static characteristics
Table 17. Static characteristics VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Supply VDD IDD supply voltage supply current operating mode; no load; fSCL = 0 MHz VDD = 2.3 V VDD = 3.3 V VDD = 5.5 V Istb VPOR VIL VIH IOL IL Ci IOL standby current power-on reset voltage LOW-level input voltage HIGH-level input voltage LOW-level output current VOL = 0.4 V; VDD = 2.3 V VOL = 0.4 V; VDD = 5.0 V leakage current input capacitance VI = VDD or VSS VI = VSS
[2] [2] [2] [2]
Parameter
Conditions
Min 2.3 [1]
Typ 38 53 108 0.005 1.70 6 2.5
Max 5.5 150 150 150 1 2.0
Unit V A A A A V
no load; fSCL = 0 Hz; I/O = inputs; VI = VDD VDD = 5.5 V no load; VI = VDD or VSS -0.5 0.7VDD 20 30 -1 12 17 25 1.6 2.3 4.0 -
Input SCL; input/output SDA +0.3VDD V 5.5 +1 10 100 5 V mA mA A pF mA mA mA mA V V V pF
LED driver outputs LOW-level output current VOL = 0.5 V; VDD = 2.3 V VOL = 0.5 V; VDD = 3.0 V VOL = 0.5 V; VDD = 4.5 V IOL(tot) VOH total LOW-level output current HIGH-level output voltage VOL = 0.5 V; VDD = 4.5 V IOH = -10 mA; VDD = 2.3 V IOH = -10 mA; VDD = 3.0 V IOH = -10 mA; VDD = 4.5 V Co
[1] [2]
output capacitance
VDD must be lowered to 0.2 V in order to reset part.
Each bit must be limited to a maximum of 25 mA and the total package limited to 100 mA due to internal busing limits.
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13. Dynamic characteristics
Table 18. Dynamic characteristics Conditions Standard- mode I2C-bus Min fSCL tBUF tHD;STA tSU;STA tSU;STO tHD;DAT tVD;ACK tVD;DAT tSU;DAT tLOW tHIGH tf tr tSP SCL clock frequency bus free time between a STOP and START condition hold time (repeated) START condition set-up time for a repeated START condition set-up time for STOP condition data hold time data valid acknowledge time data valid time data set-up time LOW period of the SCL clock HIGH period of the SCL clock fall time of both SDA and SCL signals rise time of both SDA and SCL signals pulse width of spikes that must be suppressed by the input filter
[7] [5][6] [2] [3] [1]
Symbol Parameter
Fast-mode I2C-bus Min 0 1.3 0.6 0.6 0.6 0 0.1 0.1 100 1.3 0.6 20 + 0.1Cb[4] 20 + 0.1Cb[4] Max 400 0.9 0.9 300 300 50
Fast-mode Plus I2C-bus Min 0 0.5 0.26 0.26 0.26 0 0.05 0.05 50 0.5 0.26 Max 1000 0.45 0.45 120 120 50
Unit
Max 100 3.45 3.45 300 1000 50
0 4.7 4.0 4.7 4.0 0 0.3 0.3 250 4.7 4.0 -
kHz s s s s ns s s ns s s ns ns ns
[1] [2] [3] [4] [5] [6]
Minimum SCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if either SDA or SCL is held LOW for a minimum of 25 ms. Disable bus time-out feature for DC operation. tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW. tVD;DAT = minimum time for SDA data out to be valid following SCL LOW. Cb = total capacitance of one bus line in pF. A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to Table 17, VIL of the SCL signal) in order to bridge the undefined region of SCL's falling edge. The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time (tf) for the SDA output stage is specified at 250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf. Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.
[7]
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4-bit Fm+ I2C-bus low power LED driver
SDA tBUF tLOW SCL tr tf tHD;STA tSP
tHD;STA P S tHD;DAT tHIGH tSU;DAT Sr
tSU;STA
tSU;STO P
002aaa986
Fig 20. Definition of timing
protocol
START condition (S) tSU;STA
bit 7 MSB (A7) tLOW tHIGH
bit 6 (A6)
bit 1 (D1)
bit 0 (D0)
acknowledge (A)
STOP condition (P)
1 / fSCL
SCL tBUF tr tf
SDA
tHD;STA
tSU;DAT
tHD;DAT
tVD;DAT
tVD;ACK
tSU;STO
002aab285
Rise and fall times refer to VIL and VIH.
Fig 21. I2C-bus timing diagram
14. Test information
VDD open GND
VDD PULSE GENERATOR VI DUT
RT
VO
RL 500
CL 50 pF
002aab284
RL = Load resistor for LEDn. RL for SDA and SCL > 1 k (3 mA or less current). CL = Load capacitance includes jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generators.
Fig 22. Test circuitry for switching times
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15. Package outline
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm SOT505-1
D
E
A
X
c y HE vMA
Z
8
5
A2 pin 1 index
A1
(A3)
A
Lp L
1
e bp
4
detail X wM
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.45 0.25 c 0.28 0.15 D(1) 3.1 2.9 E(2) 3.1 2.9 e 0.65 HE 5.1 4.7 L 0.94 Lp 0.7 0.4 v 0.1 w 0.1 y 0.1 Z(1) 0.70 0.35 6 0
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT505-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-04-09 03-02-18
Fig 23. Package outline SOT505-1 (TSSOP8)
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HVSON8: plastic thermal enhanced very thin small outline package; no leads; 8 terminals; body 3 x 3 x 0.85 mm
SOT908-1
0
1 scale
2 mm
X
D
B
A
E
A A1 c detail X
terminal 1 index area terminal 1 index area
1
e1 e b
4
v w
M M
CAB C
C y1 C y exposed tie bar (4x)
L
Eh
exposed tie bar (4x)
8
5
Dh
DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.3 0.2 c 0.2 D(1) 3.1 2.9 Dh 2.25 1.95 E(1) 3.1 2.9 Eh 1.65 1.35 e 0.5 e1 1.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1
Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT908-1 REFERENCES IEC JEDEC MO-229 JEITA EUROPEAN PROJECTION ISSUE DATE 05-09-26 05-10-05
Fig 24. Package outline SOT908-1 (HVSON8)
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16. Handling information
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be completely safe you must take normal precautions appropriate to handling integrated circuits.
17. Soldering
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
17.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
17.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
* * * * * *
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus PbSn soldering
17.3 Wave soldering
Key characteristics in wave soldering are:
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* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities 17.4 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 25) than a PbSn process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 19 and 20
Table 19. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 20. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 25.
PCA9632_1
(c) NXP B.V. 2007. All rights reserved.
Objective data sheet
Rev. 01 -- 28 September 2007
28 of 32
NXP Semiconductors
PCA9632
4-bit Fm+ I2C-bus low power LED driver
temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 25. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
18. Abbreviations
Table 21. Acronym CDM DUT ESD HBM I2C-bus LCD LED LSB MM MSB NMOS PCB PMOS PWM RGB RGBA SMBus Abbreviations Description Charged Device Model Device Under Test ElectroStatic Discharge Human Body Model Inter-Integrated Circuit bus Liquid Crystal Display Light Emitting Diode Least Significant Bit Machine Model Most Significant Bit Negative-channel Metal Oxide Semiconductor Printed-Circuit Board Positive-channel Metal Oxide Semiconductor Pulse Width Modulation Red/Green/Blue Red/Green/Blue/Amber System Management Bus
PCA9632_1
(c) NXP B.V. 2007. All rights reserved.
Objective data sheet
Rev. 01 -- 28 September 2007
29 of 32
NXP Semiconductors
PCA9632
4-bit Fm+ I2C-bus low power LED driver
19. Revision history
Table 22. Revision history Release date 20070928 Data sheet status Objective data sheet Change notice Supersedes Document ID PCA9632_1
PCA9632_1
(c) NXP B.V. 2007. All rights reserved.
Objective data sheet
Rev. 01 -- 28 September 2007
30 of 32
NXP Semiconductors
PCA9632
4-bit Fm+ I2C-bus low power LED driver
20. Legal information
20.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
20.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
20.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to
20.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V.
21. Contact information
For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com
PCA9632_1
(c) NXP B.V. 2007. All rights reserved.
Objective data sheet
Rev. 01 -- 28 September 2007
31 of 32
NXP Semiconductors
PCA9632
4-bit Fm+ I2C-bus low power LED driver
22. Contents
1 2 3 4 5 6 6.1 6.2 7 7.1 7.1.1 7.1.2 7.1.3 7.1.4 7.2 7.3 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.3.6 7.3.7 7.3.8 7.4 7.5 7.6 7.7 8 8.1 8.1.1 8.2 8.3 9 10 11 12 13 14 15 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Device addresses . . . . . . . . . . . . . . . . . . . . . . . 5 Regular I2C-bus slave address . . . . . . . . . . . . . 5 LED All Call I2C-bus address . . . . . . . . . . . . . . 5 LED Sub Call I2C-bus addresses . . . . . . . . . . . 5 Software Reset I2C-bus address . . . . . . . . . . . 6 Control register . . . . . . . . . . . . . . . . . . . . . . . . . 6 Register definitions . . . . . . . . . . . . . . . . . . . . . . 8 Mode register 1, MODE1 . . . . . . . . . . . . . . . . . 8 Mode register 2, MODE2 . . . . . . . . . . . . . . . . . 9 PWM registers 0 to 3, PWMx--Individual brightness control registers . . . . . . . . . . . . . . . 9 Group duty cycle control, GRPPWM . . . . . . . 10 Group frequency, GRPFREQ . . . . . . . . . . . . . 11 LED driver output state, LEDOUT . . . . . . . . . 11 I2C-bus subaddress 1 to 3, SUBADRx . . . . . . 11 LED All Call I2C-bus address, ALLCALLADR. 12 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 12 Software Reset . . . . . . . . . . . . . . . . . . . . . . . . 13 Using the PCA9632 with and without external drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Individual brightness control with group dimming/blinking . . . . . . . . . . . . . . . . . . . . . . . 15 Characteristics of the I2C-bus. . . . . . . . . . . . . 16 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 START and STOP conditions . . . . . . . . . . . . . 16 System configuration . . . . . . . . . . . . . . . . . . . 17 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 17 Bus transactions . . . . . . . . . . . . . . . . . . . . . . . 18 Application design-in information . . . . . . . . . 21 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 21 Static characteristics. . . . . . . . . . . . . . . . . . . . 22 Dynamic characteristics . . . . . . . . . . . . . . . . . 23 Test information . . . . . . . . . . . . . . . . . . . . . . . . 24 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 25 Handling information. . . . . . . . . . . . . . . . . . . . 27 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 17.1 17.2 17.3 17.4 18 19 20 20.1 20.2 20.3 20.4 21 22 Introduction to soldering. . . . . . . . . . . . . . . . . Wave and reflow soldering . . . . . . . . . . . . . . . Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 27 27 28 29 30 31 31 31 31 31 31 32
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 28 September 2007 Document identifier: PCA9632_1

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